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LE25U20AMB
WEN (bit 1)
The WEN register is for detecting whether the device can perform write operations. If it is set to "0", the device will not
perform the write operation even if the write command is input. If it is set to "1", the device can perform write
operations in any area that is not block-protected.
WEN can be controlled using the write enable and write disable commands. By inputting the write enable command
(06h), WEN can be set to "1"; by inputting the write disable command (04h), it can be set to "0". In the following states,
WEN is automatically set to "0" in order to protect against unintentional writing.
? At power-on
? Upon completion of small sector erase, sector erase or chip erase
? Upon completion of page program
? Upon completion of status register write
* If a write operation has not been performed inside the LE25U20AMB because, for instance, the command input for
any of the write operations (small sector erase, sector erase, chip erase, page program, or status register write) has
failed or a write operation has been performed for a protected address, WEN will retain the status established prior to
the issue of the command concerned. Furthermore, its state will not be changed by a read operation.
BP0, BP1 (bits 2, 3)
Block protect BP0 and BP1 are status register bits that can be rewritten, and the memory space to be protected can be
set depending on these bits. For the setting conditions, refer to "Table 4 Protect level setting conditions".
Table 4 Protect Level Setting Conditions
Protect Level
BP1
Status Register Bits
BP0
Protected Area
0 (Whole area unprotected)
1 (1/4 protected)
2 (1/2 protected)
3 (Whole area protected)
0
0
1
1
0
1
0
1
None
30000h to 3FFFFh
20000h to 3FFFFh
00000h to 3FFFFh
* Chip erase is enabled only when the protect level is 0.
SRWP (bit 7)
Status register write protect SRWP is the bit for protecting the status registers, and its information can be rewritten.
When SRWP is "1" and the logic level of the WP pin is low, the status register write command is ignored, and status
registers BP0, BP1, and SRWP are protected. When the logic level of the WP pin is high, the status registers are not
protected regardless of the SRWP state. The SRWP setting conditions are shown in "Table 5 SRWP setting conditions".
Table 5 SRWP Setting Conditions
WP Pin
0
1
SRWP
0
1
0
1
Status Register Protect State
Unprotected
Protected
Unprotected
Unprotected
Bits 4, Bits 5, and Bits 6 are reserved bits, and have no significance.
No.A2097-9/21
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